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CS5302 Two-Phase Buck Controller with Integrated Gate Drivers and 4-Bit DAC
The CS5302 is a two-phase step down controller which incorporates all control functions required to power high performance processors and high current power supplies. Proprietary multi-phase architecture guarantees balanced load current distribution and reduces overall solution cost in high current applications. Enhanced V2TM control architecture provides the fastest possible transient response, excellent overall regulation, and ease of use. The CS5302 multi-phase architecture reduces output voltage and input current ripple, allowing for a significant reduction in inductor values and a corresponding increase in inductor current slew rate. This approach allows a considerable reduction in input and output capacitor requirements, as well as reducing overall solution size and cost. Features * Enhanced V2 Control Method * 4-Bit DAC with 1% Accuracy * Adjustable Output Voltage Positioning * 4 On-Board Gate Drivers * 200 kHz to 800 kHz Operation Set by Resistor * Current Sensed through Buck Inductors, Sense Resistors, or V-S Control * Hiccup Mode Current Limit * Individual Current Limits for Each Phase * On-Board Current Sense Amplifiers * 3.3 V, 1.0 mA Reference Output * On/Off Control (through Soft Start Pin) * Power Good Output with Internal Delay
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28 1
SO-28L DW SUFFIX CASE 751F
MARKING DIAGRAM
28 CS5302 AWLYYWW 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week
PIN CONNECTIONS
COMP VFB VDRP CS1 CS2 CSREF PWRGD N/C VID0 VID1 VID2 VID3 ILIM REF 1 28 ROSC VCCL VCCL1 Gate(L)1 GND1 Gate(H)1 VCCH1 LGND SS VCCL2 Gate(L)2 GND2 Gate(H)2 VCCH2
ORDERING INFORMATION
Device CS5302GDW28 CS5302GDWR28 Package SO-28L SO-28L Shipping 27 Units/Rail 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2006
July, 2006 - Rev.7
1
Publication Order Number: CS5302/D
CS5302
+5.0 V +12 V 1.0 F ENABLE 61.9 k COMP VFB VDRP CS1 CS2 CSREF PWRGD N/C VID0 VID1 VID2 VID3 ILIM REF ROSC VCCL VCCL1 GATE(L)1 GND1 GATE(H)1 VCCH1 LGND SS VCCL2 Gate(L)2 GND2 Gate(H)2 VCCH2 Q3 300 nH + 1.0 F Q1 Q2 + +
6SP680M VOUT
1.0 nF 7.5 k 25.5 k
1.0 nF
Q4
470 nH
CS5302
12.7 k
8x 4SP820M 12 x 10 F cer
PWRGD VID0 VID1 VID2 VID3
0.1 F
4.32 k 1.0 k 25.5 k .01 F 25.5 k .01 F
0.1 F
Q5
Q6
Q7
Q8
470 nH
.01 F
Figure 1. Application Diagram, 5.0 V to 1.6 V, 35 A Converter
ABSOLUTE MAXIMUM RATINGS*
Rating Operating Junction Temperature Lead Temperature Soldering: Storage Temperature Range ESD Susceptibility (Human Body Model) 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value 150 230 peak -65 to +150 2.0 Unit C C C kV
ABSOLUTE MAXIMUM RATINGS
Pin Name Power for Logic Power for Gate(L)1 Power for Gate(L)2 Power Gate(H)1 Power for Gate(H)2 Power Good Output Pin Symbol VCCL VCCL1 VCCL2 VCCH1 VCCH2 PWRGD VMAX 16 V 16 V 16 V 20 V 20 V 6.0 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE N/A N/A N/A N/A N/A 1.0 mA ISINK 50 mA 1.5 A, 1.0 s 200 mA DC 1.5 A, 1.0 s 200 mA DC 1.5 A, 1.0 s 200 mA DC 1.5 A, 1.0 s 200 mA DC 20 mA
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ABSOLUTE MAXIMUM RATINGS (continued)
Pin Name Soft Start Capacitor Voltage Feedback Compensation Network Voltage Feedback Input Output for Adjusting Adaptive Voltage Position Frequency Resistor Reference Output High-Side FET Drivers Pin Symbol SS COMP VFB VDRP ROSC REF GATE(H) VMAX 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 20 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V DC -2.0 V for 100 ns -0.3 V DC -2.0 V for 100 ns N/A -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.5 A, 1.0 s 200 mA DC ISINK 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 50 mA 1.5 A, 1.0 s 200 mA DC
Low Side FET Drivers
GATE(L)
16 V
1.5 A, 1.0 s 200 mA DC
1.5 A, 1.0 s 200 mA DC
Return for Logic Return for #1 Driver Return for #2 Driver Current Sense for Phases 1-2 Current Limit Set Point Current Sense Reference Voltage ID DAC Inputs
LGND GND1 GND2 CS1-CS2 ILIM CSREF VID0-3
N/A 0.3 V 0.3 V 6.0 V 6.0 V 6.0 V 6.0 V
50 mA 2.0 A, 1.0 s 200 mA DC 2.0 A, 1.0 s 200 mA DC 1.0 mA 1.0 mA 1.0 mA 1.0 mA
N/A N/A N/A 1.0 mA 1.0 mA 1.0 mA 1.0 mA
ELECTRICAL CHARACTERISTICS (0C < TA < 70C; 0C < TJ < 125C; 4.7 V < VCCL < 14 V; 10 V < VCCH < 20 V;
CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 32.4 k, CCOMP = 1.0 nF, CSS = 0.1 F, CREF = 0.1 F, DAC Code 1001, CVCC = 1.0 F, ILIM 1.0 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit
Voltage Identification DAC (0 = Connected to VSS; 1 = Open or Pull-up to 3.3 V) Accuracy (all codes) VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 Not Allowed Not Allowed - - - - - - - - - - - 1.287 1.337 1.386 1.436 1.485 1.535 1.584 1.634 1.683 1.733 1.782 - - 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 - - 1.313 1.364 1.414 1.465 1.515 1.566 1.616 1.667 1.717 1.768 1.818 - - V V V V V V V V V V V V - Measure VFB = COMP 1.0 %
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CS5302
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 4.7 V < VCCL < 14 V; 10 V < VCCH < 20 V; CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 32.4 k, CCOMP = 1.0 nF, CSS = 0.1 F, CREF = 0.1 F, DAC Code 1001, CVCC = 1.0 F, ILIM 1.0 V; unless otherwise specified.)
Characteristic Test Conditions Min Typ Max Unit
Voltage Identification DAC (0 = Connected to VSS; 1 = Open or Pull-up to 3.3 V) 0 0 0 0 0 0 1 0 0 0 1 0 Not Allowed Not Allowed Not Allowed VID3, VID2, VID1, VID0 VID3, VID2, VID1, VID0 - - - - 1.00 25 3.15 - - - 1.25 50 3.30 - - - 1.50 100 3.45 - - - V k V
Input Threshold Input Pull-up Resistance Pull-up Voltage Power Good Output Power Good Fault Delay Output Low Voltage Output Leakage Current Lower Threshold Upper Threshold Voltage Feedback Error Amplifier VFB Bias Current (Note 2) COMP Source Current
CSREF = VDAC to VDAC 15% CSREF = 1.0 V, IPWRGD = 4.0 mA CSREF = 1.6 V, PWRGD = 5.5 V % of Nominal VID Code % of Nominal VID Code
25 - - -14 8
50 0.25 0.1 -11 11
125 0.40 10 -8 14
s V A % %
1.2 V < VFB < 1.9 V COMP = 0.5 V to 2.0 V; VFB = 1.75 V; DAC = 0101 COMP = 0.5 V to 2.0 V; VFB = 1.85 V; DAC = 0101 VFB = 1.75 V COMP Open; DAC = 0101 VFB = 1.85 V COMP Open; DAC = 0101 -10 A < ICOMP < +10 A - Note 3 0.01 F COMP Capacitor -
9.0 15
10.3 30
11.5 60
A A
COMP Sink Current
15
30
60
A
COMP Max Voltage COMP Min Voltage Transconductance Output Impedance Open Loop DC Gain Unity Gain Bandwidth PSRR @ 1.0 kHz Soft Start Soft Start Charge Current Soft Start Discharge Current Hiccup Mode Charge/Discharge Ratio Peak Soft Start Charge Voltage Soft Start Discharge Threshold Voltage
2.4 - - - 60 - -
2.7 0.1 32 2.5 90 400 70
- 0.2 - - - - -
V V mmho M dB kHz dB
0.2 V SS 3.0 V 0.2 V SS 3.0 V - - -
15 4.0 3.0 3.3 0.20
30 7.5 4.0 4.0 0.27
50 13 - 4.2 0.34
A A - V V
2. The VFB Bias Current changes with the value of ROSC per Figure 4. 3. Guaranteed by design. Not tested in production.
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ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 4.7 V < VCCL < 14 V; 10 V < VCCH < 20 V; CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 32.4 k, CCOMP = 1.0 nF, CSS = 0.1 F, CREF = 0.1 F, DAC Code 1001, CVCC = 1.0 F, ILIM 1.0 V; unless otherwise specified.)
Characteristic PWM Comparators Minimum Pulse Width Measured from CSx to GATE(H) V(VFB) = V(CSREF) = 1.0 V, V(COMP) = 1.5 V 60 mV step applied between VCSX and VCREF V(CS1) = V(CS2) = V(VFB) = V(CSREF) = 0 V; Measure V(COMP) when GATE(H)1, (H)2, switch high - 350 515 ns Test Conditions Min Typ Max Unit
Channel Start Up Offset
0.3
0.4
0.5
V
Gate(H) and Gate(L) High Voltage (AC) Low Voltage (AC) Rise Time Gate(H)X Rise Time Gate(L)X Fall Time Gate(H)X Fall Time Gate(L)X Gate(H) to Gate(L) Delay Gate(L) to Gate(H) Delay GATE Pull-down Oscillator Switching Frequency Switching Frequency Switching Frequency ROSC Voltage Phase Delay Adaptive Voltage Positioning VDRP Output Voltage to DACOUT Offset Maximum VDRP Voltage Current Sense Amp to VDRP Gain Current Sensing and Sharing CSREF Input Bias Current CS1-CS2 Input Bias Current Current Sense Amplifiers Gain Current Sense Amp Mismatch Current Sense Amplifiers Input Common Mode Range Limit Current Sense Input to ILIM Gain Current Limit Filter Slew Rate V(CSx) = V(CSREF) = 0 V V(CSx) = V(CSREF) = 0 V - Note 4 0 (CSx - CSREF) 50 mV Note 4 0.25 V < ILIM < 1.20 V Note 4 - - 2.8 -5.0 0 5.0 4.0 0.5 0.2 3.15 - - 6.25 10 4.0 2.0 3.53 5.0 VCCL - 2 8.0 26 A A V/V mV V V/V mV/s CS1 = CS2 = CSREF, VFB = COMP Measure VDRP - COMP (CS1 = CS2) - CREF = 50 mV, VFB = COMP, Measure VDRP - COMP - -15 240 2.4 - 310 3.0 15 380 3.8 mV mV V/V Measure any phase (ROSC = 32.4 k) Note 4 Measure any phase (ROSC = 63.4 k) Note 4 Measure any phase (ROSC = 16.2 k) - - 300 150 600 - 165 400 200 800 1.0 180 500 250 1000 - 195 kHz kHz kHz V deg Note 4 Measure VCCLX - Gate(L)X or VCCHX - Gate(H)X Note 4 Measure Gate(L)X or Gate(H)X 1.0 V < GATE < 8.0 V; VCCHX = 10 V 1.0 V < GATE < 8.0 V; VCCLX = 10 V 8.0 V > GATE > 1.0 V; VCCHX = 10 V 8.0 V > GATE > 1.0 V; VCCLX = 10 V Gate(H)X < 2.0 V, Gate(L)X > 2.0 V Gate(L)X < 2.0 V, Gate(H)X > 2.0 V Force 100 A into Gate Driver with no power applied to VCCHX and VCCLX = 2 V. - - - - - - 30 30 - 0 0 35 35 35 35 65 65 1.2 1.0 0.5 80 80 80 80 110 110 1.6 V V ns ns ns ns ns ns V
4. Guaranteed by design. Not tested in production.
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CS5302
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 4.7 V < VCCL < 14 V; 10 V < VCCH < 20 V; CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 32.4 k, CCOMP = 1.0 nF, CSS = 0.1 F, CREF = 0.1 F, DAC Code 1001, CVCC = 1.0 F, ILIM 1.0 V; unless otherwise specified.)
Characteristic Current Sensing and Sharing ILIM Bias Current Single Phase Pulse by Pulse Current Limit: V(CSx) - V(CSREF) Current Share Amplifier Bandwidth Reference Output VREF Output Voltage General Electrical Specifications VCCL Operating Current VCCL1 Operating Current VCCL2 Operating Current VCCH1 Operating Current VCCH2 Operating Current VCCL Start Threshold VCCL Stop Threshold VCCL Hysteresis VCCH1 Start Threshold VCCH1 Stop Threshold VCCH1 Hysteresis VFB = COMP (no switching) VFB = COMP (no switching) VFB = COMP (no switching) VFB = COMP (no switching) VFB = COMP (no switching) GATEs switching, Soft Start charging GATEs stop switching, Soft Start discharging GATEs not switching, Soft Start not charging GATEs switching, Soft Start charging GATEs stop switching, Soft Start discharging GATEs not switching, Soft Start not charging - - - - - 4.05 3.75 100 8.4 7.8 300 20 4.0 4.0 2.8 2.5 4.4 4.2 200 9.2 8.7 500 24.5 5.5 5.5 4.0 3.5 4.7 4.6 300 9.9 9.6 700 mA mA mA mA mA V V mV V V mV 0 mA < I(VREF) < 1.0 mA 3.2 3.3 3.4 V Note 5 0 < ILIM < 1.0 V - - 90 1.0 0.1 105 - 1.0 135 - A mV MHz Test Conditions Min Typ Max Unit
5. Guaranteed by design. Not tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE PIN # 28 Lead SO Wide 1 2 PIN SYMBOL COMP VFB FUNCTION Output of the error amplifier and input for the PWM comparators. Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP) select an offset voltage at light load and connect a resistor between VFB and VOUT. The input bias current of the VFB pin and the resistor value determine output voltage offset for zero output current. Short VFB to VOUT for no AVP. Current sense output for AVP. The offset of this pin above the DAC voltage is proportional to the output current. Connect a resistor from this pin to VFB to set amount AVP or leave this pin open for no AVP. Current sense inputs. Connect current sense network for the corresponding phase to each input. Reference for current sense amplifiers and input for Power Good comparators. To balance input offset voltages between the inverting and non-inverting inputs of the current sense amplifiers, connect a resistor between CSREF and the output voltage. The value should be 2/5 of the value of the resistors connected to the CSx pins. Power Good Output. Open collector output goes low when CSREF is out of regulation.
3
VDRP
4-5 6
CS1-CS2 CSREF
7
PWRGD
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PACKAGE PIN DESCRIPTION (continued)
PACKAGE PIN # 28 Lead SO Wide 8 9-12 13 14 15 16 17 18 19 20 PIN SYMBOL N/C VID3-VID0 ILIM REF VCCH2 Gate(H)2 GND2 Gate(L)2 VCCL2 SS No connection. Voltage ID DAC inputs. These pins are internally pulled up to 3.3 V if left open. Sets threshold for current limit. Connect to reference through a resistive divider. Reference output. Decouple with 0.1 F to LGND. Power for GATE(H)2. High side driver #2. Return for #2 driver. Low side driver #2. Power for GATE(L)2. Soft Start capacitor pin. The Soft Start capacitor controls both Soft Start time and hiccup mode frequency. The COMP pin is clamped below Soft Start during Start-Up and hiccup mode. Return for internal control circuits and IC substrate connection. Power for GATE(H)1. UVLO Sense for High Side Driver supply connects to this pin. High side driver #1. Return #1 drivers. Low side driver #1. Power for GATE(L)1. Power for internal control circuits. UVLO Sense for Logic connects to this pin. A resistor from this pin to ground sets operating frequency and VFB bias current. FUNCTION
21 22 23 24 25 26 27 28
LGND VCCH1 Gate(H)1 GND1 Gate(L)1 VCCL1 VCCL ROSC
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VCCL - + DACOUT DAC Delay - + REF VID0 VID1 VID2 VID3 LGND CO1 + +11% VDRP CSREF -
AVPA Start Stop
-
3.3 V REF
+
Reset Dominant
PWMC1
- +
CO1 + -
MAXC1
+
Reset Dominant
PWMC2
- +
CO2
CS1
Set Dominant
SS Charge Current SS Discharge Current
FAULT S SS Discharge Threshold PH 1 OSC PH 2 + + - +
FAULT
R
SS
Figure 2. Block Diagram
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8
+
EA
-
ILIM
-
-
CS2
+
ILIM Filter +
+
CSA2
-
CO2
x2
Offset
DACOUT
-
-
CO2
+
CSA1
+ -
CO1
+ -11%
- +
-
+
Start Stop
- 9.2 V 8.7 V PH 1 S Gate Nonoverlap R 0.33 V FAULT PH 2 S Gate Nonoverlap R + MAXC2 - 0.33 V FAULT Current Source Gen BIAS COMP VFB ROSC
4.4 V 4.2 V
PWRGD VCCH1 Gate(H)1 VCCL1 Gate(L)1 GND1 VCCH2 Gate(H)2 VCCL2 Gate(L)2 GND2
-
-
CS5302
TYPICAL PERFORMANCE CHARACTERISTICS
900 800 700 Frequency, kHz 600 500 400 300 200 100 10 20 30 40 50 60 70 VFB Bias Current, A 25 20 15 10 5 0 10
20
30
40
50
60
70
80
ROSC Value, k
ROSC Value, k
Figure 3. Oscillator Frequency
Figure 4. VFB Bias Current vs. ROSC Value
120 100 Time, ns 80 60 40 20 0
120 100 Time, ns 80 60 40 20 0 0 2 4 6 8 10 12 14 16 Load Capacitance, nF
0
2
4
6
8
10
12
14
16
Load Capacitance, nF
Figure 5. Gate(H) Rise-time vs. Load Capacitance measured from 1.0 V to 4.0 V with VCC at 5.0 V.
Figure 6. Gate(H) Fall-time vs. Load Capacitance measured from 4.0 V to 1.0 V with VCC at 5.0 V.
120 100 Time, ns Time, ns 80 60 40 20 0 0 2 4 6 8 10 12 14 16 Load Capacitance, nF
120 100 80 60 40 20 0 0 2 4 6 8 10 12 14 16 Load Capacitance, nF
Figure 7. Gate(L) Rise-time vs. Load Capacitance measured from 4.0 V to 1.0 V with VCC at 5.0 V.
Figure 8. Gate(L) Fall-time vs. Load Capacitance measured from 4.0 V to 1.0 V with VCC at 5.0 V.
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APPLICATIONS INFORMATION FIXED FREQUENCY MULTI-PHASE CONTROL In a multi-phase converter, multiple converters are connected in parallel and are switched on at different times. This reduces output current from the individual converters and increases the apparent ripple frequency. Because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. The CS5302 uses a two-phase, fixed frequency, Enhanced V2 architecture. Each phase is delayed 180 from the previous phase. Normally GATE(H) transitions high at the beginning of each oscillator cycle. Inductor current ramps up until the combination of the current sense signal and the output ripple trip the PWM comparator and bring GATE(H) low. Once GATE(H) goes low, it will remain low until the beginning of the next oscillator cycle. While GATE(H) is high, the enhanced V2 loop will respond to line and load transients. Once GATE(H) is low, the loop will not respond again until the beginning of the next cycle. Therefore, constant frequency Enhanced V2 will typically respond within the off-time of the converter. The Enhanced V2 architecture measures and adjusts current in each phase. An additional input (Cx) for inductor current information has been added to the V2 loop for each phase as shown in Figure 9. inductor starts the cycle with a higher current, the PWM cycle will terminate earlier providing negative feedback. The CS5302 provides a Cx input for each phase, but the CSREF, VFB and COMP inputs are common to all phases. Current sharing is accomplished by referencing all phases to the same VFB and COMP pins, so that a phase with a larger current signal will turn off earlier than phases with a smaller current signal. Including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. When the average output current is zero, the COMP pin will be only 1/2 of the steady state ramp height plus the OFFSET above the output voltage. If the COMP pin is held steady and the inductor current changes, there must also be a change in the output voltage. Or, in a closed loop configuration when the output current changes, the COMP pin must move to keep the same output voltage. The required change in the output voltage or COMP pin depends on the scaling of the current feedback signal and is calculated as
DV + RS CSA Gain DI CSA Gain.
The single-phase power stage output impedance is:
Single Stage Impedance + DV DI + RS
SWNODE
L
RL RS
CX
+
CSA
+ + +
OFFSET CSREF
The multi-phase power stage output impedance is the single-phase output impedance divided by the number of phases. The output impedance of the power stage determines how the converter will respond during the first few s of a transient before the feedback loop has repositioned the COMP pin. The peak output current of each phase can also be calculated from;
V * VFB * VOFFSET Ipkout (per phase) + COMP RS CSA Gain
VOUT
+
VFB DACOUT
+ E.A. +
+
PWMCOMP
COMP
Figure 9. Enhanced V2 Feedback and Current Sense Scheme
The inductor current is measured across RS, amplified by CSA and summed with the OFFSET and Output Voltage at the non-inverting input of the PWM comparator. The inductor current provides the PWM ramp and as inductor current increases the voltage on the positive pin of the PWM comparator rises and terminates the PWM cycle. If the
Figure 10 shows the step response of a single phase with the COMP pin at a fixed level. Before T1 the converter is in normal steady state operation. The inductor current provides the PWM ramp through the Current Sense Amplifier. The PWM cycle ends when the sum of the current signal, voltage signal and OFFSET exceed the level of the COMP pin. At T1 the output current increases and the output voltage sags. The next PWM cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the VFB pin and the cycle ends at T2. After T2 the output voltage remains lower than at light load and the current signal level is raised so that the sum of the current and voltage signal is the same as with the original load. In a closed loop system the COMP pin would
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move higher to restore the output voltage to the original level. winding resistance at higher temperatures should be considered when setting the ILIM threshold. If a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in Figure 9.
Current Sharing Accuracy
SWNODE
VFB (VOUT)
CSA Out
COMP - Offset CSA Out + VFB T1 T2
Figure 10. Open Loop Operation Inductive Current Sensing
For lossless sensing, current can be sensed across the inductor as shown in Figure 11. In the diagram L is the output inductance and RL is the inherent inductor resistance. To compensate the current sense signal the values of R1 and C1 are chosen so that L/RL = R1 x C1. If this criteria is met the current sense signal will be the same shape as the inductor current, the voltage signal at Cx will represent the instantaneous value of inductor current and the circuit can be analyzed as if a sense resistor of value RL was used as a sense resistor (RS).
SWNODE L C1 RL VOUT CSREF VFB DACOUT COMP
E.A. +
PCB traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. For accurate current sharing, the current sense inputs should sense the current at the same point for each phase and the connection to the CSREF should be made so that no phase is favored. (In some cases, especially with inductive sensing, resistance of the pcb can be useful for increasing the current sense resistance.) The total current sense resistance used for calculations must include any pcb trace between the CS inputs and the CSREF input that carries inductor current. Current Sense Amplifier Input Mismatch and the value of the current sense element will determine the accuracy of current sharing between phases. The worst case Current Sense Amplifier Input Mismatch is 5.0 mV and will typically be within 3.0 mV. The difference in peak currents between phases will be the CSA Input Mismatch divided by the current sense resistance. If all current sense elements are of equal resistance a 3.0 mV mismatch with a 2.0 m sense resistance will produce a 1.5 A difference in current between phases.
Operation at > 50% Duty Cycle
R1 CS
+ CSA
+ + + +
For operation at duty cycles above 50% Enhanced V2 will exhibit subharmonic oscillation unless a compensation ramp is added to each phase. A circuit like the one on the left side of Figure 12 can be added to each current sense network to implement slope compensation. The value of R1 can be varied to adjust the ramp size.
Gate(L)X Switch Node
OFFSET
PWMCOMP
3k
R1
25 k CSX
Figure 11. Lossless Inductive Current Sensing with Enhanced V2
1.0 nF 0.1 F MMBT2222LT1 Slope Comp Circuit
.01 F CSREF
When choosing or designing inductors for use with inductive sensing tolerances and temperature, effects should be considered. Cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. Copper magnet wire has a temperature coefficient of 0.39% per C. The increase in
Existing Current Sense Circuit
Figure 12. External Slope Compensation Circuit
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Ramp Size and Current Sensing
Because the current ramp is used for both the PWM ramp and to sense current, the inductor and sense resistor values will be constrained. A small ramp will provide a quick transient response by minimizing the difference over which the COMP pin must travel between light and heavy loads, but a steady state ramp of 25 mVp-p or greater is typically required to prevent pulse skipping and minimize pulse width jitter. For resistive current sensing, the combination of the inductor and sense resistor values must be chosen to provide a large enough steady state ramp. For large inductor values the sense resistor value must also be increased. For inductive current sensing, the RC network must meet the requirement of L/RL = R x C to accurately sense the AC and DC components of the current the signal. Again the values for L and RL will be constrained in order to provide a large enough steady state ramp with a compensated current sense signal. A smaller L, or a larger RL than optimum might be required. But unlike resistive sensing, with inductive sensing, small adjustments can be made easily with the values of R and C to increase the ramp size if needed. If RC is chosen to be smaller (faster) than L/RL, the AC portion of the current sensing signal will be scaled larger than the DC portion. This will provide a larger steady state ramp, but circuit performance will be affected and must be evaluated carefully. The current signal will overshoot during transients and settle at the rate determined by R x C. It will eventually settle to the correct DC level, but the error will decay with the time constant of R x C. If this error is excessive it will effect transient response, adaptive positioning and current limit. During transients the COMP pin will be required to overshoot along with the current signal in order to maintain the output voltage. The VDRP pin will also overshoot during transients and possibly slow the response. Single phase overcurrent will trip earlier than it would if compensated correctly and hiccup mode current limit will have a lower threshold for fast rise step loads than for slowly rising output currents. The waveforms in Figure 13 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of L = 500 nH, RL = 1.6 m, R1 = 20 k and C1 = .01 F. For ideal current signal compensation the value of R1 should be 31 k. Due to the faster than ideal RC time constant there is an overshoot of 50% and the overshoot decays with a 200 s time constant. With this compensation the ILIM pin threshold must be set more than 50% above the full load current to avoid triggering hiccup mode during a large output load step.
Figure 13. Inductive Sensing waveform during a Step with Fast RC Time Constant (50 s/div) Current Limit
Two levels of overcurrent protection are provided. Any time the voltage on a Current Sense pin exceeds CSREF by more than the Single Phase Pulse by Pulse Current Limit, the PWM comparator for that phase is turned off. This provides fast peak current protection for individual phases. The outputs of all the currents are also summed and filtered to compare an averaged current signal to the voltage on the ILIM pin. If this voltage is exceeded, the fault latch trips and the Soft Start capacitor is discharged by a 7.5 A source until the COMP pin reaches 0.2 V. Then Soft Start begins. The converter will continue to operate in this mode until the fault condition is corrected.
Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of the normal operation of the Enhanced V2 control topology with synchronous rectifiers. The control loop responds to an overvoltage condition within 400 ns, causing the top MOSFET's to shut off and the synchronous MOSFET's to turn on. This results in a "crowbar" action to clamp the output voltage and prevent damage to the load. The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low.
Transient Response and Adaptive Positioning
For applications with fast transient currents the output filter is frequently sized larger than ripple currents require in
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order to reduce voltage excursions during transients. Adaptive voltage positioning can reduce peak-peak output voltage deviations during load transients and allow for a smaller output filter. The output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is stepped up and set lower than nominal during heavy loads to reduce overshoot when the load current is stepped up. For low current applications a droop resistor can provide fast accurate adaptive positioning. However, at high currents the loss in a droop resistor becomes excessive. For example; in a 50 A converter a 1.0 m resistor to provide a 50 mV change in output voltage between no load and full load would dissipate 2.5 Watts. Lossless adaptive positioning is an alternative to using a droop resistor, but must respond quickly to changes in load current. Figure 14 shows how adaptive positioning works. The waveform labeled normal shows a converter without adaptive positioning. On the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. With fast (ideal) adaptive positioning the peak to peak excursions are cut in half. In the slow adaptive positioning waveform the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. to the final voltage after a transient. This will be most apparent with lower capacitance output filters. Note: Large levels of adaptive positioning can cause pulse width jitter.
Error Amp Compensation
The transconductance error amplifier requires a capacitor between the COMP pin and GND. Use of values less than 1nF may result in error amp oscillation of several MHz. The capacitor between the COMP pin and the inverting error amplifier input and the parallel resistance of the VFB resistor and the VDRP resistor are used to roll off the error amp gain. The gain is rolled off at a high enough frequency to give a quick transient response, but low enough to cross zero dB well below the switching frequency to minimize ripple and noise on the COMP pin.
UVLO
The CS5302 has undervoltage lockout functions connected to two pins. One, intended for the logic and low-side drivers, with a 4.4 V turn-on threshold is connected to the VCCL pin. A second, intended for the high side drivers, powered from 12 V has a 9.0 V threshold is connected to the VCCH1 pin. Both thresholds must be exceeded for the converter to start.
Soft Start and Hiccup Mode
Normal Fast Adaptive Positioning Slow Adaptive Positioning Limits
Figure 14. Adaptive Positioning
The CS5302 can be configured to adjust the output voltage based on the output current of the converter. (Refer to the application diagram on page 2.) To set the no-load positioning, a resistor is placed between the output voltage and VFB pin. The VFB bias current will develop a voltage across the resistor to increase the output voltage. The VFB bias current is dependent on the value of ROSC. See Figure 4. During no load conditions the VDRP pin is at the same voltage as the VFB pin, so none of the VFB bias current flows through the VDRP resistor. When output current increases the VDRP pin increases proportionally and the VDRP pin current offsets the VFB bias current and causes the output voltage to decrease. The VFB and VDRP pins take care of the slower and DC voltage positioning. The first few s are controlled primarily by the ESR and ESL of the output filter. The transition between fast and slow positioning is controlled by the ramp size and the error amp compensation. If the ramp size is too large or the error amp too slow there will be a long transition
A capacitor between the Soft Start pin and GND controls Soft Start and hiccup mode slopes. A 0.1 F capacitor with the 30 A charge current will allow the output to ramp up at 0.3 V/ms or 1.5 V in 5.0 ms at start-up. When a fault is detected due to overcurrent or UVLO the converter will enter a low duty cycle hiccup mode. During hiccup mode the converter will not switch from the time a fault is detected until the Soft Start capacitor has discharged below the Soft Start Discharge Threshold and then charged back up above the Channel Start Up Offset. The Soft Start pin will disable the converter when pulled below 0.3 V.
Layout Guidelines
With the fast rise, high output currents of microprocessor applications, parasitic inductance and resistance should be considered when laying out the power, filter and feedback signal sections of the board. Typically, a multi-layer board with at least one ground plane is recommended. If the layout is such that high currents can exist in the ground plane underneath the controller or control circuitry, the ground plane can be slotted to reroute the currents away from the controller. The slots should typically not be placed between the controller and the output voltage or in the return path of the gate drive. Additional power and ground planes or islands can be added as required for a particular layout. Gate drives experience high di/dt during switching and the inductance of gate drive traces should be minimized. Gate
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drive traces should be kept as short and wide as practical and should have a return path directly below the gate trace. Output filter components should be placed on wide planes connected directly to the load to minimize resistive drops during heavy loads and inductive drops and ringing during transients. If required, the planes for the output voltage and return can be interleaved to minimize inductance between the filter and load. Voltage feedback should be taken from a point of the output or the output filter that doesn't favor any one phase. If the feedback connection is closer to one inductor than the others the ripple associated with that phase may appear larger than the ripple associated with the other phases and poor current sharing can result. The current sense signal is typically tens of milli-volts. Noise pick-up should be avoided wherever possible. Current feedback traces should be routed away from noisy areas such as switch nodes and gate drive signals. The paths should be matched as well as possible. It is especially important that all current sense signals be picked off at similar points for accurate current sharing. If the current signal is taken from a place other than directly at the inductor any additional resistance between the pick-off point and the inductor appears as part of the inherent inductor resistance and should be considered in design calculations. Capacitors for the current feedback networks should be placed as close to the current sense pins as practical. DESIGN PROCEDURE
Current Sensing, Power Stage and Output Filter Components
For ideal current sense compensation the ratio of L and RL is fixed, so the values of L and RL will be a compromise typically with the maximum value RL limited by conduction losses or inductor temperature rise and the minimum value of L limited by ripple current. 3. For resistive current sensing choose L and RS to provide a steady state ramp greater than 25 mV.
L RS + (VIN * VOUT) TON 25 mV
Again the ratio of L and RL is fixed and the values of L and RS will be a compromise. 4. Calculate the high frequency output impedance (ConverterZ) of the converter during transients. This is the impedance of the Output filter ESR in parallel with the power stage output impedance (PwrstgZ) and will indicate how far from the original level (VR) the output voltage will typically recover to within one switching cycle. For a good transient response VR should be less than the peak output voltage overshoot or undershoot.
DVR + ConverterZ ConverterZ + ESR PwrstgZ ESR PwrstgZ ) ESR CSA Gain 3.0
where:
PwrstgZ + RS
1. Choose the output filter components to meet peak transient requirements. The formula below can be used to provide an approximate starting point for capacitor choice, but will be inadequate to calculate actual values.
DVPEAK + (DI DT) ESL ) DI ESR
Multiply the converterZ by the output current step size to calculate where the output voltage should recover to within the first switching cycle after a transient. If the ConverterZ is higher than the value required to recover to where the adaptive positioning is set the remainder of the recovery will be controlled by the error amp compensation and will typically recover in 10-20 s.
DVR + DIOUT ConverterZ
Ideally the output filter should be simulated with models including ESR, ESL, circuit board parasitics and delays due to switching frequency and converter response. Typically both bulk capacitance (electrolytic, Oscon, etc.,) and low impedance capacitance (ceramic chip) will be required. The bulk capacitance provides "hold up" during the converter response. The low impedance capacitance reduces steady state ripple and bypasses the bulk capacitance during slewing of output current. 2. For inductive current sensing (only) choose the current sense network RC to provide a 25 mV minimum ramp during steady state operation.
R + (VIN * VOUT) VOUT VIN F C 25 mV
Make sure that VR is less than the expected peak transient for a good transient response. 5. Adjust L and RL or RS as required to meet the best combination of transient response, steady state output voltage ripple and pulse width jitter.
Current Limit
When the sum of the Current Sense amplifiers (VITOTAL) exceeds the voltage on the ILIM pin the part will enter hiccup mode. For inductive sensing the ILIM pin voltage should be set based on the inductor resistance (or current sense resistor) at max temperature and max current. To set the level of the ILIM pin: 6. VI(LIM) + R IOUT(LIM) CS to ILIM Gain where: R is RL or RS; IOUT(LIM) is the current limit threshold.
Then choose the inductor value and inherent resistance to satisfy L/RL = R x C.
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For the overcurrent to work properly the inductor time constant (L/R) should be the Current sense RC. If the RC is too fast, during step loads the current waveform will appear larger than it is (typically for a few hundred s) and may trip the current limit at a level lower than the DC limit.
Adaptive Positioning
4.00 3.50 Frequency, kHz 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 10 5 1/ Apparent Duty Cycle 15
7. To set the amount of voltage positioning below the DAC setting at no load connect a resistor (RV(FB)) between the output voltage and the VFB pin. Choose RV(FB) as;
RV(FB) + NL Position VFB Bias Current
Figure 15. Normalized Input Filter Capacitor Ripple Current
See Figure 4 for VFB Bias Current. 8. To set the difference in output voltage between no load and full load, connect a resistor (RV(DRP)) between the VDRP and VFB pins. RV(DRP) can be calculated in two steps. First calculate the difference between the VDRP and VFB pin at full load. (The VFB voltage should be the same as the DAC voltage during closed loop operation.) Then choose the RV(DRP) to source enough current across RV(FB) for the desired change in output voltage.
DVV(DRP) + IOUTFL R CS to VDRP Gain
DESIGN EXAMPLE Choose the component values for a 5.0 V to 1.6 V, 35 A converter with lossless current sensing, adaptive positioning and a 45 A current limit. The adaptive positioning is chosen 30 mV above the nominal VOUT at no load and 40 mV below the no-load position with 35 A out. The peak output voltage transient is 70 mV max during a 32 A step current.
Current Sensing, Power Stage and Output Filter Components
where: R = RL or RS for one phase; IOUTFL is the full load output current.
RV(DRP) + DVDRP RV(FB) DVOUT
1. Assume 1.5 m of output filter ESR. 2.
R + (VIN * VOUT) + (5.0 * 1.6) + 17.4 kW L RL + .01 mF 17.47 kW + 174 ms Choose RL + 2.0 mW L + 2.0 mW 174 ms + 348 nH VOUT VIN C 25 mV 1.6 5.0 250 k 0.01 mF 25 mV F
Calculate Input Filter Capacitor Current Ripple
The procedure below assumes that phases do not overlap and output inductor ripple current (P-P) is less than the average output current of one phase. 9. Calculate Input Current
IIN + VOUT IOUT (Efficiency VIN)
3. n/a 4.
PwrstgZ + RL CSA Gain 2.0 + 2.0 mW 3.15 2.0 + 3.1 mW ConverterZ + PwrstgZ ESR PwrstgZ ) ESR + 3.1 mW 1.5 mW ^ 1.0 mW 3.1 mW ) 1.5 mW DVR + 1.0 mW 32 A + 32 mV
10. Calculate Duty Cycle (per phase).
VOUT Duty Cycle + (Efficiency VIN)
11. Calculate Apparent Duty Cycle.
Apparent Duty Cycle + Duty Cycle # of Phases
12. Calculate Input Filter Capacitor Ripple Current. Use the chart in Figure 15 to calculate the normalized ripple current (KRMS) based on the reciprocal of Apparent Duty Cycle. Then multiply the input current by KRMS to obtain the Input Filter Capacitor Ripple Current.
Ripple (RMS) + IIN KRMS
5. n/a
Current Limit
6.
VI(LIM) + RL IOUT(LIM) CS to ILIM Gain + 2.0 mW 45 A 6.25 + 562 mV
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Adaptive Positioning
9.
IIN + 1.52 V
7.
RV(FB) + NL Position VFB Bias Current + 30 mV 6.0 mA + 5.0 kW
10.
Duty Cycle +
0.85
41 A + 6.1 A 12VIN
8.
DVDRP + RL IOUT Current Sense to VDRP Gain + 2.0 mW 35 A 3.0 + 210 mV RV(DRP) + DVDRP + 210 mV + 26 kW RV(FB) DVOUT 5.0 kW 40 mV
11. 12.
1.52 V + 0.15 0.85 12 VIN 2.0 + 0.3
Apparent Duty Cycle + 0.15 RMS ripple + 6.1 A
1.5 + 9.2 A
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PACKAGE DIMENSIONS
SO-28L DW SUFFIX CASE 751F-05 ISSUE F
A D
28 15 M NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H L q MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0_ 8_
E
H
1 PIN 1 IDENT 14
B
A
0.25
M
B
e B 0.025
M
A1
0.10 C
SEATING PLANE
L C q
CA
S
B
S
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical 28 Lead SO Wide 15 75 Unit C/W C/W
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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CS5302/D

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